The present invention generally relates to an analog-to-digital converter (“ADC”) and, more particularly, to an inverter-based flash ADC including a floating resistor ladder for use, for example, in ultra wideband (“UWB”) transceivers.
An analog-to-digital converter (“ADC”) is a device for converting an input analog signal, either in the form of a voltage or current, into a digital signal. ADCs are typically divided into successive approximation ADCs and flash ADCs. A successive approximation ADC functions to sequentially determine bits of a digital code corresponding to an analog input. Generally, a successive approximation ADC requires one clock cycle per bit of resolution. On the other hand, a flash ADC, which includes a more complicated hardware structure than the successive approximation ADC, is able to complete the entire analog-to-digital conversion process simultaneously rather than sequentially, generally in only one clock cycle.
Of the flash ADCs, an inverter-based flash ADC, which employs the TIQ (threshold-inverter-quantization) technique, meets the requirements of low power consumption and low supply voltage in SOC (system-on-chip) designs. The TIQ technique is advantageous in that it can be integrated with other digital circuits while reducing total power consumption. Such an advantage renders the TIQ technique suitable for use in UWB (ultra wideband) transceivers, in which low power consumption is a matter of concern. However, conventional flash ADCs generally suffer from inverter mismatch, which may occur due to unsymmetry in the fabrication of the inverters of the ADC, disadvantageously resulting in variations in the switching threshold voltages of the inverters. The switching threshold voltage Vm of an inverter is given below.Vm=[r(VDD−|VTp|)+VTn]/(1+r)
where VDD is the supply voltage of the inverter-based flash ADC, VTp and VTn are the threshold voltages of the PMOS and NMOS transistors of the inverter, respectively, and r is further defined below.r=[μP×COX×(W/L)P)]1/2/[μN×COX×(W/L)N)]1/2
where μP and μN are the mobility of hole and electron, respectively, COX refers to a capacitance of an oxide film, and (W/L)P and (W/L)N are the channel width to channel length ratios of the PMOS and NMOS transistors of the inverter, respectively.
To overcome the inverter mismatch issue, conventional techniques have been proposed to adjust the factors of Vm, including VDD, VTp, VTn and the W/L ratio. In a first approach of the conventional techniques, a supply voltage VDD to be connected to each of the comparators of a flash ADC varies as the Vm varies such that the supply voltage level at one comparator may be different from that at another comparator. In a second approach, the doping density in the transistors of each of the comparators varies such that doping density may be different from comparator to comparator. In a third approach, the W/L ratio in the transistors varies such that the size may be different from comparator to comparator. The first and second approaches, which may have proposed a linear solution, have difficulty in implementation. The third approach may be disadvantageous in layout design and has difficulty in providing transistors with individual threshold voltages.
It is desirable to have a flash ADC that addresses inverter mismatch without changing the size or parameters of the inverters, while retaining the features of an inverter-based flash ADC such as low power consumption as required by a UWB transceiver.